1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed at an interface positioned between highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration in the drain and source regions, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice in the near future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different silicon regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has preferably been used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling, in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions, to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. That is, conventionally, the thickness of the silicon dioxide layer has been correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials in combination with the high-k dielectric material. The conventional approach to incorporate P-type dopants into the gate electrode of the P-channel transistor and N-type dopants into the gate electrode of the N-channel transistor is less than desirable, since a depletion zone may form at the vicinity of the gate dielectric/polysilicon interface, which in turn may increase the effective thickness of the gate dielectric, thereby reducing the capacitive coupling.
For replacing the doped polysilicon at least at this interface, appropriate metal-containing materials may be provided to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided.
The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence in order to adjust an appropriate work function for the transistors of different conductivity type and due to the fact that high-k dielectric materials and the conductive cap materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function, and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in critical gate openings is required.
In other very promising approaches, the sophisticated gate electrode structures having the desired work function are formed in an early manufacturing stage, while the further processing is based on many well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques.
Due to the ongoing demand for shrinking the gate length of transistors, very complex patterning regimes based on hard mask materials have typically been applied. Since a plurality of different materials are present in the complex gate layer stack, i.e., the gate insulation layer including the high-k dielectric material, a metal-containing cap layer, which, depending on the selected process strategy, may comprise two or more individual material layers, followed by the silicon material and a dielectric cap material, which may be acquired in addition to a hard mask material for appropriately patterning the gate layer stack in accordance with the design rules, the finally obtained shape and gate length may depend on any differences between the gate layer stacks of P-channel transistors and N-channel transistors. In addition to any patterning-related non-uniformities of gate electrode structures formed on the basis of a high-k dielectric material in combination with an electrode material including a metal-containing material and a silicon material, a certain degree of performance reduction in view of the AC behavior of sophisticated transistors has been observed, which is believed to be caused by the interface between the silicon material and the metal-containing cap layer, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, which comprises complementary transistors 150A, 150B, i.e., a P-channel transistor and an N-channel transistor, respectively, at an early manufacturing stage. As illustrated, a gate electrode structure 160A is formed on a semiconductor region or active region 102A, while a gate electrode structure 160B is formed on an active region 102B. In this context, active regions are to be understood as semiconductor regions in which are formed or are to be formed appropriate PN junctions so as to act as drain and source regions of the transistors 150A, 150B, respectively. The active regions 102A, 102B are formed in a silicon-based semiconductor layer 102, which in turn is formed above a substrate 101, which represents any appropriate carrier material, such as a semiconductor material and the like. The semiconductor layer 102 typically comprises isolation structures (not shown) which laterally delineate the active regions 102A, 102B in accordance with device requirements. Furthermore, if required, a buried insulating material (not shown) may be formed between the substrate 101 and the semiconductor layer 102, thereby forming a silicon-on-insulator (SOI) configuration. The gate electrode structures 160A, 160B typically have a similar configuration and comprise a gate insulation layer 163, which comprises a first dielectric material 161, for instance provided in the form of a silicon dioxide-based material, such as a silicon oxynitride material, with a thickness of one nanometer and less in order to not unduly contribute to a reduced capacitive coupling, as explained above. Moreover, the gate insulation layer 163 typically comprises a high-k dielectric material 162, such as hafnium oxide, zirconium oxide and the like, which may have a significantly greater dielectric constant compared to the material 161 so that, in total, a physically greater thickness of the gate insulation material 163 may be obtained, while, nevertheless, the desired high capacitive coupling is achieved. Furthermore, a metal-containing electrode material or cap material 164 is formed on the gate insulation layer 163 and is comprised of any appropriate material, such as titanium nitride and the like, possibly in combination with additional metal species, as required. Furthermore, a silicon material 165 is formed on the metal-containing cap layer 164 and, thus, the silicon material 165 may form an interface 164I with the metal-containing material 164.
Additionally, the gate electrode structure 160A comprises the dielectric cap layer 166, for instance comprised of silicon nitride, silicon dioxide and the like. Moreover, a sidewall spacer 167, such as a silicon nitride material, is formed on the sidewalls of the materials 165, 164, and 163. In principle, the gate electrode structure 160B may have substantially the same configuration, except for modifications in the gate insulation layer 163 and/or the metal-containing cap material 164 in order to obtain an appropriate effective work function of the material 164, thereby adjusting the threshold voltages of the transistors 150A, 150B. That is, as discussed above, in complex transistor elements, a dopant concentration in channel regions 151 of the transistors may be reduced in order to avoid undue charge carriers scattering and, thus, the final threshold voltages may essentially be determined by the work function of the gate electrode materials. To this end, the metal-containing cap layers 164 may have incorporated therein an appropriate metal species, such as aluminum and the like for P-channel transistors, and lanthanum and the like for N-channel transistors, which may result in the desired work function and, thus, the threshold voltage. In other approaches, an appropriate metal species may be incorporated in the gate insulation layer 163, thereby creating fixed dipole charges, which may result, in combination with the overlying metal-containing material 164, in the desired electronic characteristics. In this case, the material 164 may be selected identically for the gate electrode structures 160A, 160B, as long as the different characteristics in the gate insulation layers 163 may provide the desired threshold voltages.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of any appropriate process strategy. That is, after providing the active regions 102A, 102B based on process techniques for fabricating isolation structures and providing a basic dopant concentration in the regions 102A, 102B, the gate insulation material 163 may be formed by deposition, oxidation and the like as required for providing the materials 161 and 162. Next, appropriate metal species may be formed above the active regions 102A, 102B in order to appropriately adjust the resulting work function, which may include the initiation of diffusion processes in order to diffuse specific metal species into the underlying gate insulation layer 163, while, in other cases, appropriate materials may be positioned above the gate insulation layer 163. Finally, the conductive cap material 164 is formed above the active regions 102A, 102B and may, depending on the process strategy, have the same composition or may be different for the gate electrode structures 160A, 160B. Thereafter, the silicon material 165 is deposited, followed by the deposition of a cap material 166, for instance in the form of silicon nitride and the like. Thereafter, any further materials, such as hard mask materials, for instance in the form of amorphous carbon and the like, in combination with the resist material, are provided above the resulting layer stack and are used to pattern the layer stack. For this purpose, the resist material may be used to pattern the hard mask material and the dielectric cap material 166, which is then used as an efficient mask for etching through the silicon material 165 and finally through the materials 164 and 163. Thereafter, the spacer element 167 is formed, for instance, by depositing a silicon nitride material and etching the same in order to reliably confine the materials 163 and 164, which may react very sensitively to certain process conditions and in particular to exposure to oxygen.
The further processing is then continued, for instance, by removing the cap layer 166, forming drain and source extension regions, possibly in combination with additional offset spacer elements, and finally a further sidewall spacer structure is provided in order to form drain and source regions.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the transistors 150A, 150B comprise drain and source regions 152, in which metal silicide regions 153 are provided to reduce the overall resistance of the transistors 150A, 150B. It should be appreciated that the drain and source regions 152 of the transistor 150A are of inverse conductivity type compared to the drain and source regions 152 of the transistor 150B. Moreover, a metal silicide 168 is also formed in the silicon material 165, thereby further enhancing overall conductivity of the gate electrode structures 160A and 160B. As explained above, the drain and source regions 152 may be formed on the basis of a sidewall spacer structure 154, which is used as an implantation mask together with the gate electrode structures 160A, 160B. Furthermore, as is well known, an appropriate masking regime is to be applied so as to implant appropriate dopant species for the transistors 150A, 150B, which may be accomplished by providing resist masks in accordance with well-established process techniques. Thereafter, high temperature processes are applied to activate the dopants and re-crystallize implantation-induced damage, thereby obtaining the final dopant profile of the drain and source regions 152. Next, the metal silicide regions 168 and 153 are formed on the basis of any appropriate silicidation sequence, wherein any appropriate material, such as nickel silicide, cobalt silicide, platinum silicide and the like, may be formed.
Upon operating the transistors 150A, 150B, it has been observed that in particular, the AC resistivity of the gate electrode structures 160A, 160B may be higher than expected, which is believed to be caused by the interface 164I between the material 164 and the polysilicon material 165. The interface 164I may represent a Schottky barrier, which may, thus, affect the high frequency behavior of the gate electrode structures 150A, 150B. Moreover, the characteristics of the interface 164I may further be deteriorated upon contact with oxygen during the entire process sequence for forming the transistors 150A, 150B, since, due to the oxygen affinity of the material 164, a certain degree of oxygen agglomeration may occur. Since, generally, the Schottky barrier may be lowered by providing a moderately high dopant concentration in the semiconductor material, it has been proposed, in addition to any dopant species introduced during the implantation sequences for forming the drain and source regions 152, to provide a certain degree of predoping of the material 165.
Again referring to FIG. 1a, as illustrated, the gate electrode structures 160A, 160B may comprise predoped areas 165A, 165B, respectively, which may be obtained on the basis of an implantation process, thereby also creating an increased dopant concentration in the vicinity of the interface 164I. As previously discussed, however, due to the doped areas 165A, 165B including dopant of different conductivity types, the resulting patterning process may be significantly influenced due to the different etch behavior of doped silicon material relative to undoped silicon material, and in particular when different types of dopants are used. For example, when adjusting the etch chemistry to suppress a substantially lateral etch rate for a non-doped or lightly doped silicon material, a pronounced lateral etch rate may occur in the doped area 165A, thereby resulting in “under etched” areas, as indicated by 165C. Similarly, different etch behavior may also be created in the doped region 165B, which may thus result in a non-uniform cross-sectional shape of each of the gate electrode structures 160A, 160B, while a difference in the shape may also occur between the gate electrode structures 160A, 160B.
Consequently, although predoping of the silicon material may result in an increased dopant concentration at the interface 164I, thereby lowering the Schottky barrier, the conventional approach may contribute to additional non-uniformities of the gate electrode structures, in particular for complementary transistors.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.